AN725 データシートの表示（PDF） - Silicon Laboratories

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AN725

ADVANCED LOW POWER TECHNIQUES FOR SiM3L1XX DEVICES

Silicon Laboratories 

AN725

5. Reducing Power Consumption in Low Power Modes

In low power mode, the device core halts and the number of active peripherals typically reduces to the minimum

required by the application (i.e., real time clock). This section discusses techniques to reduce the SiM3L1xx device

power consumption in low power modes (PM2, PM3, PM6, and PM8).

5.1. SiM3L1xx Low Power Mode Overview

The SiM3L1xx devices feature seven low power modes in addition to normal operating mode. Several peripherals

provide wake up sources for these low power modes, including the Low Power Timer (LPTIMER0), RTC0 (alarms

and oscillator failure notification), Comparator 0 (CMP0), Advanced Capture Counter (ACCTR0), LCD VBAT

monitor (LCD0), UART0, low power mode charge pump failure, and PMU Pin Wake.

In addition, all peripherals can have their clocks disabled to reduce power consumption with the clock control

(CLKCTRL) registers whenever a peripheral is not being used.

The SiM3L1xx devices have the power modes defined in Table 2.

5.1.1. Normal Mode (Power Mode 0)

Normal mode encompasses the typical full-speed operation. The power consumption of the device in this mode will

vary depending on AHB/APB clock speeds, the settings of CLKCTRL and the peripherals, and the dc-dc converter

and LDO settings.

5.1.2. Power Mode 1

Power Mode 1 occurs when the core executes code from RAM instead of flash. The power consumption of the

device is less than normal mode when in PM1.

5.1.3. Power Mode 2

In Power Mode 2, the core halts and the peripherals run at full speed. To place the device in this mode, the clock

settings in CLKCTRL should remain the same as Normal or Power Mode 1 and the core should execute a WFI or

WFE instruction. If the WFI instruction is called from an interrupt service routine, the interrupt that wakes the device

from PM2 must be of a sufficient priority to be recognized by the core. It is recommended to perform both a DSB

(Data Synchronization Barrier) and an ISB (Instruction Synchronization Barrier) operation prior to the WFI to

ensure all bus access is complete.

5.1.4. Power Mode 3 Fast Wake

Power Mode 3 Fast Wake occurs when all the clocks are stopped except for the LFOSC0 or RTC0TCLK. The core

and the peripherals are halted in this mode. The available wake up sources to wake from PM3 are controlled by the

Power Management Unit (PMU). The available wake up sources are: Low Power Timer (LPTIMER0), RTC0

(alarms and oscillator failure notification), Comparator 0 (CMP0), advanced capture counter (ACCTR0), LCD VBAT

monitor (LCD0), UART0, and PMU Pin Wake. Any reset event will also wake the device from PM3.

If the WFI instruction that wakes the device from PM3 Fast Wake is called from an interrupt service routine, the

interrupt that wakes the device from PM3FW must be of a sufficient priority to be recognized by the core.

By keeping the core clock running at a slow frequency in PM3 and changing the AHB and APB clocks to the Low

Power Oscillator, the device can wake up faster than in standard Power Mode 3 at the expense of higher power

consumption.

5.1.5. Power Mode 3

Power Mode 3 occurs when all the clocks are stopped, and the core and the peripherals are halted. Waking from

PM3 requires one of the PMU wake sources described in “5.1.4. Power Mode 3 Fast Wake” to be properly

configured.

If the WFI instruction is called from an interrupt service routine, the interrupt that wakes the device from PM3 must

be of a sufficient priority to be recognized by the core.

5.1.6. Power Mode 4

Power Mode 4 is the same as normal operation except the AHB clock operates at a slower speed. The power

consumption of the device in this mode will vary depending on the AHB/APB clock speeds, the settings of

CLKCTRL and the peripherals, and the dc-dc converter and LDO settings.

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