AN725 データシートの表示（PDF） - Silicon Laboratories

部品番号

コンポーネント説明

メーカー

AN725

ADVANCED LOW POWER TECHNIQUES FOR SiM3L1XX DEVICES

Silicon Laboratories 

AN725

5.1.7. Power Mode 5

Power Mode 5 is the same as PM1 with a slower AHB clock source selected. The core executes code from RAM

instead of flash. The power consumption of the device in PM5 is slightly less than PM4.

5.1.8. Power Mode 6

In Power Mode 6, the core halts and the peripherals run at a slower speed than PM2. To place the device in this

mode, the clock settings in CLKCTRL should remain the same as PM4 or PM5, and the core should execute a WFI

or WFE instruction. If the WFI instruction is called from an interrupt service routine, the interrupt that wakes the

device from PM6 must be of a sufficient priority to be recognized by the core.

5.1.9. Power Mode 8

In Power Mode 8, the core and most peripherals are halted, most clocks are stopped, and registers retain their

state. In addition, the LDO regulators are disabled, so all active circuitry operates directly from VBAT. Alternatively,

the PMU has a specialized VBAT-divided-by-2 low power mode charge pump that can power some internal

modules while in PM8 to save power. The fully operational functions in this mode are: LPTIMER0, RTC0, UART0

running from RTC0TCLK, port match, advanced capture counter, and the LCD controller.

This mode provides the lowest power consumption for the device, but requires an appropriate wake up source or

reset to exit. The available wake up or reset sources to wake from PM8 are controlled by the Power Management

Unit (PMU). The available wake up sources are: Low Power Timer (LPTIMER0), RTC0 (alarms and oscillator

failure notification), Comparator 0 (CMP0), advanced capture counter (ACCTR0), LCD VBAT monitor (LCD0),

UART0, low power mode charge pump failure, and PMU Pin Wake. The available reset sources are: RESET pin,

VBAT supply monitor, Comparator 0, Comparator 1, low power mode charge pump failure, RTC0 oscillator failure,

or PMU wake event.

To enter this mode, firmware must write the SLEEPDEEP bit in the ARM System Control Register. Firmware must

then execute a WFI or WFE instruction. The core will remain in PM8 until an enabled wake up or reset source

occurs.

8

Rev. 0.1

Share Link: