AN725 データシートの表示（PDF） - Silicon Laboratories
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AN725 Datasheet PDF : 28 Pages
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AN725
Table 2. SiM3L1xx Power Modes
Mode
Description
Mode Entrance
Mode Exit
Normal
Core operating at full speed
Code executing from flash
Power Mode 1 Core operating at full speed
(PM1)
Code executing from RAM
Execute code from RAM Jump to code in flash
Core halted
Power Mode 2
(PM2)
AHB and APB operate at full
speed for peripherals
WFI or WFE instruction
NVIC or WIC wakeup
All clocks stopped except LFOSC0 DMACTRL0 disabled
or RTC0TCLK
Power Mode 3 AHB and APB set to Low Power
Fast Wake
Oscillator
(PM3FW)
Core clock set to LFOSC0 or
Fast wake mode
enabled in PM3CN
AHB switched to Low
Power Oscillator
RTC0TCLK
WFI or WFE instruction
Requires a wake up
source or reset defined by
the PMU
Power Mode 3
(PM3)
All clocks stopped
DMACTRL0 disabled
Clocks disabled in
PM3CN
WFI or WFE instruction
Requires a wake up
source or reset defined by
the PMU
Power Mode 4 Core operating at slower speed
(PM4)
Code executing from flash
Set the AHB clock to a
slower source
Set the AHB clock to a
faster source
Core operating at slower speed
Power Mode 5
(PM5)
Code executing from RAM
Set the AHB clock to a
slower source
Execute code from RAM
Set the AHB clock to a
faster source or jump to
code in flash
Core halted
Set the AHB clock to a
Power Mode 6
(PM6)
AHB and APB operate at a slower
slower source
speed for peripherals
WFI or WFE instruction
NVIC or WIC wakeup
Low power sleep
The LDO regulators are disabled
and all active circuitry operates
directly from VBAT
SLEEPDEEP set in the
ARM System Control
Register
WFI or WFE instruction
Power Mode 8 The following functions are
(PM8)
available: ACCTR0, RTC0, UART0
running from RTC0TCLK,
LPTIMER0, port match, and the
LCD controller
Register state retention
Requires a wake up
source or reset defined by
the PMU
Rev. 0.1
9
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