ADMC326 データシートの表示（PDF） - Analog Devices
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ADMC326 Datasheet PDF : 31 Pages
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ADMC326
• SPORT1 receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• SPORT1 can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1), and the Flag In and Flag Out signals.
The internally generated serial clock may still be used in this
configuration.
• SPORT1 has two data receive pins (DR1A and DR1B), which
are internally multiplexed onto the one DR1 port of the
SPORT1. The particular data receive pin selected is deter-
mined by a bit in the MODECTRL register.
PIN FUNCTION DESCRIPTION
The ADMC326 is available in a 28-lead SOIC package and a
28-lead PDIP package. Table I describes the pins.
Table I. Pin List
memory RAM and ROM are provided on the ADMC326. Pro-
gram memory RAM is arranged as one contiguous 512 × 24-bit
block, starting at address 0x0000. Program memory ROM is a
4K × 24-bit block located at address 0x0800. Data memory is
arranged as a 512 × 16-bit block starting at address 0x3800. The
motor control peripherals are memory mapped into a region of
the data memory space starting at 0x2000. The complete program
and data memory maps are given in Tables II and III, respectively.
Table II. Program Memory Map
Address Range
0x0000–0x002F
0x0030–0x01FF
0x0200–0x07FF
0x0800–0x17FF
0x1800–0x3FFF
Memory
Type Function
RAM
RAM
ROM
Interrupt Vector Table
User Program Memory
Reserved
User Program Memory
Reserved
Group
Name
# of Input/
Pins Output Function
RESET
SPORT11
1I
6 I/O
CLKOUT1
1O
CLKIN, XTAL 2 I, O
PIO0–PIO81
9 I/O
AUX0–AUX11 2 O
AH–CL
PWMTRIP
6O
1I
V1, V2, V3
3I
VAUX0–VAUX2 3 I
ICONST
1O
VDD
1
GND
1
Processor Reset Input
Serial Port 1 Pins (TFS1,
RFS1, DT1, DR1A, DR1B,
SCLK1)
Processor Clock Output
External Clock or Quartz
Crystal Connection Point
Digital I/O Port Pins
Auxiliary PWM Outputs
PWM Outputs
PWM Trip Signal
Analog Inputs
Auxiliary Analog Input
ADC Constant Current Source
Power Supply
Ground
Table III. Data Memory Map
Address Range
0x0000–0x1FFF
0x2000–0x20FF
0x2100–0x37FF
0x3800–0x39FF
0x3A00–0x3BFF
0x3C00–0x3FFF
Memory
Type
RAM
RAM
Function
Reserved
Memory Mapped Registers
Reserved
User Data Memory
Reserved
Memory Mapped Registers
SYSTEM INTERFACE
Figure 4 shows a basic system configuration for the ADMC326
with an external crystal.
CLKOUT XTAL
33pF
10MHz
NOTE
1Multiplexed pins, selectable individually through the PIOSELECT and
PIODATA1 registers.
CLKIN
ADMC326
33pF
INTERRUPT OVERVIEW
The ADMC326 can respond to 16 different interrupt sources
with minimal overhead, five of which are internal DSP core
interrupts and 11 are from the motor control peripherals. The five
DSP core interrupts are SPORT1 receive (or IRQ0) and trans-
mit (or IRQ1), the internal timer, and two software interrupts.
The motor control peripheral interrupts are the nine program-
mable I/Os and two from the PWM (PWMSYNC pulse and
PWMTRIP). All motor control interrupts are multiplexed into the
DSP core through the peripheral IRQ2 interrupt. The interrupts
are internally prioritized and individually maskable. A detailed
description of the entire interrupt system of the ADMC326 is
presented later, following a more detailed description of each
peripheral block.
Memory Map
The ADMC326 has two distinct memory types: program memory
and data memory. In general, program memory contains user
code and coefficients, while the data memory is used to store
variables and data during program execution. Both program
RESET
Figure 4. Basic System Configuration
Clock Signals
The ADMC326 can be clocked either by a crystal or a TTL-
compatible clock signal. For normal operation, the CLKIN
input cannot be halted, changed during operation, or operated
below the specified minimum frequency. If an external clock is
used, it should be a TTL-compatible signal running at half the
instruction rate. The signal is connected to the CLKIN pin of
the ADMC326. In this mode, with an external clock signal, the
XTAL pin must be left unconnected. The ADMC326 uses an
input clock with a frequency equal to half the instruction rate;
a 10 MHz input clock yields a 50 ns processor cycle (which is
equivalent to 20 MHz). Normally, instructions are executed in a
single processor cycle. All device timing is relative to the internal
instruction rate, which is indicated by the CLKOUT signal
when enabled.
Because the ADMC326 includes an on-chip oscillator feedback
circuit, an external crystal may be used instead of a clock source, as
REV. A
–9–
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