ST93CS56M1013TR データシートの表示（PDF） - STMicroelectronics

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ST93CS56M1013TR

2K (128 x 16) SERIAL MICROWIRE EEPROM

STMicroelectronics 

ST93CS56

ST93CS57

2K (128 x 16) SERIAL MICROWIRE EEPROM

NOT FOR NEW DESIGN

1 MILLION ERASE/WRITE CYCLES, with

40 YEARS DATA RETENTION

SELF-TIMED PROGRAMMING CYCLE with

AUTO-ERASE

READY/BUSY SIGNAL DURING

PROGRAMMING

SINGLE SUPPLY VOLTAGE

– 3V to 5.5V for the ST93CS56

– 2.5V to 5.5V for the ST93CS57

USER DEFINED WRITE PROTECTED AREA

PAGE WRITE MODE (4 WORDS)

SEQUENTIAL READ OPERATION

5ms TYPICAL PROGRAMMING TIME

ST93CS56 and ST93CS57 are replaced by

the M93S56

8

1

PSDIP8 (B)

0.4mm Frame

8

1

SO8 (M)

150mil Width

Figure 1. Logic Diagram

DESCRIPTION

The ST93CS56 and ST93CS57 are 2K bit Electri-

cally Erasable Programmable Memory (EEPROM)

fabricated with SGS-THOMSON’s High Endurance

Single Polysilicon CMOS technology. The memory

is accessed through a serial input D and output Q.

The 2K bit memory is organized as 128 x 16 bit

words.The memory is accessed by a set of instruc-

tions which include Read, Write, Page Write, Write

All and instructions used to set the memory protec-

tion. A Read instruction loads the address of the

first word to be read into an internal address

pointer.

Table 1. Signal Names

S

Chip Select Input

D

Serial Data Input

Q

Serial Data Output

C

Serial Clock

PRE

W

Protect Enable

Write Enable

VCC

Supply Voltage

VSS

Ground

D

C

S

PRE

W

VCC

ST93CS56

ST93CS57

VSS

Q

AI00896B

June 1997

This is information on a product still in production bu t not recommended for new de signs.

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