X24C02MI-2.7 データシートの表示（PDF） - Xicor -> Intersil

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X24C02MI-2.7

Serial E2PROM

Xicor -> Intersil 

X24C02

Sequential Read

Sequential Read can be initiated as either a current

address read or random access read. The first word is

transmitted as with the other modes, however, the

master now responds with an acknowledge, indicating it

requires additional data. The X24C02 continues to out-

put data for each acknowledge received. The master

terminates this transmission by issuing a stop condition,

omitting the ninth clock cycle acknowledge.

Figure 9. Sequential Read

The data output is sequential, with the data from address

n followed by the data from n + 1. The address counter

for read operations increments all address bits, allowing

the entire memory contents to be serially read during

one operation. At the end of the address space (address

255), the counter “rolls over” to address 0 and the

X24C02 continues to output data for each acknowledge

received. Refer to Figure 9 for the address, acknowl-

edge and data transfer sequence.

SLAVE

BUS ACTIVITY: ADDRESS

MASTER

SDA LINE

A

BUS ACTIVITY:

C

X24C02

K

DATA n

A

A

A

C

C

C

K

K

K

DATA n+1

DATA n+2

Figure 10. Typical System Configuration

DATA n+x

S

T

O

P

P

3838 FHD F15

VCC

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER

3838 FHD F16

8

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