24LCS61(1997) データシートの表示（PDF） - Microchip Technology
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24LCS61 Datasheet PDF : 16 Pages
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24LCS61/62
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the start signal from the master, the control
byte for a write command is sent by the master trans-
mitter. The device will acknowledge this control byte
during the ninth clock pulse. The next byte transmitted
by the master is the ID byte for the device. After receiv-
ing another acknowledge signal from the 24LCS61/62,
the master device will transmit the address and then
the data word to be written into the addressed memory
location. The 24LCS61/62 acknowledges between
each byte, and the master then generates a stop con-
dition. This initiates the internal write cycle, and during
this time the 24LCS61/62 will not generate acknowl-
edge signals (Figure 6-1).
6.2 Page Write
The control byte, ID byte, word address, and the first
data byte are transmitted to the 24LCS61/62 in the
same way as in a byte write. But, instead of generating
a stop condition, the master transmits up to 15 addi-
tional data bytes to the 24LCS61/62, which are tempo-
rarily stored in the on-chip page buffer and will be
written into the memory after the master has transmit-
ted a stop condition. If the master should transmit more
than 16 bytes prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 6-2) and the 24LCS61/
62 will not generate acknowledge.
6.3 Low Voltage Write Protection
The 24LCS61/62 employs a VCC threshold detector cir-
cuit which disables the internal erase/write logic, if the
VCC is below 1.5 volts at nominal conditions.
6.4 Set Write Protection Command
The Set Write Protection command allows the user to
write protect a portion of the array. For the 24LCS61
this command will write protect the entire array. For the
24LCS62 this command will protect the lower half of
the array. This command is illustrated in Figure 6-3.
This is a one time only command and cannot be
reversed once the protection fuse has been set.
Once the Write protect feature has been set, the device
will no longer acknowledge the control byte (or any of
the other bytes) of this command. The STOP bit of this
command initiates an internal write cycle, and during
this time the 24LCS61/62 will not generate acknowl-
edge signals.
FIGURE 6-1: BYTE WRITE
BUS ACTIVITY
MASTER
S
T CONTROL
A
BYTE
R
T
DEVICE
ID BYTE
ADDRESS
BYTE
S
T
O
DATA
P
SDA LINE
S
0
1
1
0
O
E
0
1
0
BUS ACTIVITY
A
A
A
A
C
C
C
C
OE Bit = EDS Pin Output Enable; see Section 9.0
K
K
K
K
FIGURE 6-2:
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
PAGE WRITE
S
T
A CONTROL
R
BYTE
T
S
0
1
1
0
O
E
0
1
0
A
C
K
DEVICE
ID BYTE
ADDRESS
BYTE
DATA BYTE 0
A
A
A
C
C
C
K
K
K
S
T
DATA BYTE 15 O
P
A
C
K
FIGURE 6-3:
SET WRITE PROTECTION COMMAND
S
T
A CONTROL
R
BYTE
T
S
0
1
1
0
O
E
0
0
0
A
C
K
DEVICE
ID BYTE
ADDRESS
BYTE
S
DATA BYTE
T
O
P
XXXXXXXX XXXXXXXX P
A
A
A
C
C
C
K
K
K
DS21226A-page 10
Preliminary
© 1997 Microchip Technology Inc.
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