24LCS61(1997) データシートの表示（PDF） - Microchip Technology
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24LCS61 Datasheet PDF : 16 Pages
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24LCS61/62
TABLE 1-3: AC CHARACTERISTICS
All parameters apply across the specified
operating ranges unless otherwise noted.
Vcc = +2.5V to 5.5V
Commercial (C):
Industrial (I):
Tamb = 0°C to +70°C
Tamb = -40°C to +85°C
Parameter
VCC = 2.5V - 5.5V Vcc = 4.5V - 5.5V
Symbol STD MODE
FAST MODE Units
Remarks
Min. Max. Min. Max.
Clock frequency
FCLK
—
100
—
400 kHz
Clock high time
THIGH 4000
—
600
—
ns
Clock low time
TLOW 4700
—
1300
—
ns
SDA and SCL rise time
TR
—
1000
—
300 ns From VIL to VIH (Note 1)
SDA and SCL fall time
TF
—
300
—
300 ns From VIL to VIH (Note 1)
START condition hold time THD:STA 4000
—
600
—
ns After this period the first
clock pulse is generated
START condition setup time TSU:STA 4700
—
600
—
ns Only relevant for repeated
START condition
Data input hold time
THD:DAT
0
—
0
—
ns (Note 2)
Data input setup time
TSU:DAT 250
—
100
—
ns
STOP condition setup time TSU:STO 4000
—
600
—
ns
Output valid from clock
TAA
—
3500
—
900 ns (Note 2)
Bus free time
TBUF 4700
—
1300
—
ns Time the bus must be free
before a new transmission
can start
Output fall time
TOF
(from 0.7 VCC to 0.3 VCC)
Input filter spike suppression TSP
(SDA and SCL pins)
—
250 20 +0.1 250
ns (Note 1), CB ≤ 100 pF
CB
—
50
—
50
ns (Notes 1, 3)
Write cycle time
TWC
—
10
—
10
ms Byte or Page mode
Endurance
10M
—
10M
— cycles 25°C, VCC = 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise
spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-1: BUS TIMING DATA
SCL
SDA
IN
SDA
OUT
TF
Tsu:sta
THD:STA
TSP
TLOW
THIGH
THD:DAT
TR
TSU:DAT
TSU:STO
TAA
TBUF
© 1997 Microchip Technology Inc.
Preliminary
DS21226A-page 3
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