24LCS61(1997) データシートの表示（PDF） - Microchip Technology
部品番号
コンポーネント説明
メーカー
24LCS61 Datasheet PDF : 16 Pages
| |||
24LCS61/62
5.0 ASSIGNING THE ID BYTE
The 24LCS61/62 device contains a special register
which holds an 8-bit ID byte that is used as an address
to communicate with a specific device on the bus. All
read and write commands to the device must include
this ID address byte. Upon power-up, the ID byte will
default to 00h. Communicating with the device using
the default address is typically done only at testing or
programming time and not when it is connected to a
bus with more than one device. Before the device can
be used on a common bus with other devices, a unique
ID byte address must be assigned to every device.
5.1 Assign Address Command
The ID byte is assigned by sending the Assign Address
command. This command queries any device con-
nected to the bus and utilizing the automatic bus arbi-
tration feature, assigns an ID byte to the device that
remains on the bus after arbitration is complete. Once
a device has been assigned an ID byte, it will no longer
respond to Assign Address commands until power is
cycled or the Clear Address command is sent. The
Assign Address command must be repeated for each
device on the bus until all devices have been assigned
an ID byte.
The format for the Assign Address command is shown
in Figure 5-1. The command consists of the control
byte, the ID byte to be assigned to the device remaining
when the arbitration is complete, and 48 bits of data
being transmitted by devices on the bus. If the OE bit is
set to a 1, then any device who has not been assigned
an address will assert their respective EDS pin after the
acknowledge bit following the Device ID byte. After the
control byte and ID byte are sent, each device will begin
to transmit its unique 48-bit serial number. The
24LCS61/62 must acknowledge the control byte and
the device ID byte, and the master must acknowledge
each byte of the serial number transmitted by the
device. As each bit is clocked out, each device will
monitor the bus to detect if another device is also trans-
mitting. If any device is outputting a logic ‘1’ on the bus
and it detects that the bus is at a logic ‘0’, then it
assumes that another device is controlling the bus. As
soon as any device detects that it is not controlling the
bus it will immediately stop transmitting data and return
to standby mode. The master must end the command
by sending a no ack after all 6 bytes of the serial num-
ber have been transmitted, followed by a Stop bit.
Sending the Stop bit in any other position of the com-
mand will result in the command aborting and all
devices releasing the bus with no address assigned. If
a device transmits its entire 48 bit serial number without
releasing the bus to another device, then the ID byte
transmitted within the command is transferred to the
internal ID byte register upon receipt of the Stop bit and
it will now respond only to commands that contain this
ID byte (or the Clear Address command). Once a
device has been assigned an ID byte, it will no longer
respond to Assign Address commands until power is
cycled or the Clear Address command is sent.
This process of assigning ID bytes is repeated by the
controller until no more devices respond to the Assign
Address command. At this point, all devices on the bus
have been assigned an ID byte and standard read and
write commands can be executed to each individual
device.
The ID byte is stored in a volatile SRAM register, and if
power is removed from the device or the Clear Address
command is sent, then the ID byte will default to
address 00 and the process of assigning an ID value
must be repeated.
FIGURE 5-1: ASSIGN ADDRESS COMMAND
A unique address must be assigned to each
device on the bus
STOP bit must occur here
or command will abort
S
T
6 Bytes (48 Bits) of Device Serial Number
S
A CONTROL
with each byte separated by an ack bit
T
R
BYTE
Device ID Byte
O
T
P
S
0
1
1
0
O
E
1
0
0
P
A
A
A
A
N
C
C
C
C
O
K
K
K
K
A
C
K
© 1997 Microchip Technology Inc.
Preliminary
DS21226A-page 7
Share Link: 