24LCS61 データシートの表示（PDF） - Microchip Technology
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24LCS61 Datasheet PDF : 22 Pages
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24LCS61/24LCS62
2.0 PIN DESCRIPTIONS
2.1 SDA (Serial Data)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
The SDA pin has Schmitt Trigger and filter circuits
which suppress noise spikes to assure proper device
operation even on a noisy bus
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1 Bus not Busy (A)
Both data and clock lines remain high.
2.2 SCL (Serial Clock)
This input is used to synchronize the data transfer from
and to the device. The SCL pin has Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
2.3 EDS (External Device Select)
The External Device Select (EDS) pin is an open drain
output that is controlled by using the OE bit in the
control byte. It can be used to enable other circuitry
when the device is selected. A pull-up resistor must be
added to this pin for proper operation. This pin should
not be pulled up to a voltage higher than Vcc+1V. See
Section 9.0 “External Device Select (EDS) Pin and
Output Enable (OE) Bit” for more details.
3.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
FIGURE 3-1:
SCL (A) (B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D)
(D)
(C) (A)
SDA
START
CONDITION
DATA OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
DS21226E-page 4
2004 Microchip Technology Inc.
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