APU3073 データシートの表示（PDF） - Advanced Power Electronics Corp
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コンポーネント説明
メーカー
APU3073
Advanced Power Electronics Corp
APU3073 Datasheet PDF : 17 Pages
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APU3073
PIN#
12
13
14
15
16
PIN SYMBOL
PGnd
Gnd
HDrv
VcH
OCSet
PIN DESCRIPTION
This pin serves as the separate ground for MOSFET's driver and should be connected to
system's ground plane.
This pin serves as analog ground for internal reference and control circuitry. A high fre-
quency capacitor must be connected from Vcc pin to this pin for noise free operation.
Output driver for the high side power MOSFET. This pin should not go negative (below
ground), this may cause problem for the gate drive circuit. It can happen when the inductor
current goes negative (Source/Sink), soft-start at no load and for the fast load transient
from full load to no load. To prevent negative voltage at gate drive, a low forward voltage
drop diode might be connected between this pin and ground.
This pin is connected to a voltage that must be at least 4V higher than the bus voltage of
the switcher (assuming 5V threshold MOSFET) and powers the high side output driver. A
minimum of 1mF, high frequency capacitor must be connected from this pin to ground to
provide peak drive current capability.
This pin is connected to the Drain of the lower MOSFET via an external resister and it
provides the positive sensing for the internal current sensing circuitry. The external resis-
tor programs the current limit threshold depending on the RDS(ON) of the power MOSFET.
An external capacitor can be placed in parallel with the programming resistor to provide
high frequency noise filtering.
BLOCK DIAGRAM
Vcc 9
20uA
3V
Vcc 4.2V / 4.0V
Bias
Generator
3V
1.25V
POR
UVLO
SS/SD 4
POR
Comp 5
VP1 7
Fb1 6
3V
OCSet 16
VcH 3.5V / 3.3V
64uA
Max
25K
25K
20uA
CS Comp
Error Amp
Rt
Oscillator
Ct
En
Error Comp
0.4V
S
Q
R
Reset Dom
POR
FbLo Comp
Vcc
0.8V
TSD
Fb2 1
1.25V
0.8V 8 VREF
3 Rt
15 VcH
14 HDrv
10 VcL
11 LDrv
12 PGnd
2 Drv2
13 Gnd
Figure 2 - Simplified block diagram of the APU3073.
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