AS1541 データシートの表示（PDF） - austriamicrosystems AG

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AS1541

8/4-Channel, 10-Bit I²C Analog-to-Digital Converter

austriamicrosystems AG 

AS1539/AS1541

Data Sheet - Detailed Description

Reference Voltage

The AS1539/AS1541 can operate with an internal 2.5V reference or an external reference. If a +5V supply is used, an

external +5V reference is required in order to provide full dynamic range for a 0V to +VDD analog input. The external

reference can be as low as 1V. When using a +2.7V supply, the internal +2.5V reference will provide full dynamic range

for a 0V to +2.5V analog input.

As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is often

referred to as the LSB (least significant bit) size and is equal to the reference voltage divided by 1024. This means that

any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB size, as the reference volt-

age is reduced.

Digital Interface

The AS1539/AS1541 supports the I2C serial bus and data transmission protocol in high-speed mode at 3.4MHz. The

AS1539/AS1541 operates as a slave on the I2C bus. The bus must be controlled by a master device that generates the

serial clock (SCL), controls the bus access, and generates the START and STOP conditions. Connections to the bus

are made via the open-drain I/O pins SCL and SDA.

Figure 24. Bus Protocol

SDA

SCL

START

MSB

Slave Address

R/W

Direction Bit

1

2

6

7

8

9

ACK

ACK from

Receiver

ACK from

Receiver

1

2 3-8 8

9

ACK

Repeat if More Bytes Transferred

STOP or

Repeated

START

The bus protocol (as shown in Figure 24) is defined as:

- Data transfer may be initiated only when the bus is not busy.

- During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line

while the clock line is HIGH will be interpreted as control signals.

The bus conditions are defined as:

- Bus Not Busy. Data and clock lines remain HIGH.

- Start Data Transfer. A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a

START condition.

- Stop Data Transfer. A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH,

defines the STOP condition.

- Data Valid. The state of the data line represents valid data, when, after a START condition, the data line is stable

for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data

bytes transferred between START and STOP conditions is not limited and is determined by the master device.

The information is transferred byte-wise and each receiver acknowledges with a ninth-bit.

Within the I2C bus specifications a high-speed mode (3.4MHz clock rate) is defined.

- Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the recep-

tion of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge

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