AS7C1024C データシートの表示（PDF） - Alliance Semiconductor
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AS7C1024C Datasheet PDF : 9 Pages
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AS7C1024C
®
AC test conditions
– Output load: see Figure B.
– Input pulse level: GND to 3.0 V. See Figure A.
– Input rise and fall times: 3 ns. See Figure A.
– Input and output timing reference levels: 1.5 V.
+5 V
+3.0V
90%
90%
10%
GND
3 ns
10%
Figure A: Input pulse
DOUT
255 Ω
480 Ω
C13
GND
Figure B: 5 V Output load
Thevenin equivalent:
DOUT
168 Ω
+1.728 V
Notes
1 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A and B.
4 tCLZ and tCHZ are specified with CL = 5 pF, as in Figure B. Transition is measured ±200 mV from steady-state voltage.
5 This parameter is guaranteed, but not 100% tested.
6 WE is high for read cycle.
7 CE and OE are low for read cycle.
8 Address is valid prior to or coincident with CE transition low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/A.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
12/5/06, v. 1.0
Alliance Memory
P. 6 of 9
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