AS8201 データシートの表示（PDF） - austriamicrosystems AG

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AS8201

TTP/C-C1 Communications Controller

austriamicrosystems AG 

TTP/C-C1 Communications Controller Data Sheet

AS8201

Austria Mikro Systeme International AG

lines signal to host CPU the global synchronous time of the TTP network and determine when

to deliver, resp. to fetch data from the host interface. One of the lines may be connected to a

interrupt inputs of the host CPU.

Pin Name

RAM_ADDRESS

RAM_DATA

RAM_CEB

RAM_WEB

RAM_OEB

RAM_READYB

TIME_OVERFLOW

TIME_SIGNAL

TIME_TICK

mode

in

inout (tri)

in

in

in

out

out

out

out

Table 2 Host Interface Ports

width

11

16

1

1

1

1

1

1

1

comment

DPRAM address bus, 11 bit

DPRAM data bus, 16 bit

DPRAM chip enable

DPRAM write enable

DPRAM output enable

DPRAM ready

overflow of global time

CNI time signal

macrotick

tct

microtick

trwct

tce

ram_ceb

ram_web

ram_address

ta

address stable

XXX

ram_data

Figure 3: Read Cycle Timing

XXX

tdv

Addresses and RAM_WEB have to be stable before the falling edge of RAM_CEB. RAM_CEB

has to be applied for 2 microticks. Addresses and RAM_WEB have to be applied for 3

microticks. Data can be read from RAM_DATA after 6 microticks. RAM_OEB drives the result

of the (last) read operation to the RAM_DATA bus.

Rev. NC, October 1999

Page 8 of 13

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