AS7C513B データシートの表示（PDF） - Alliance Semiconductor
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AS7C513B Datasheet PDF : 9 Pages
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AS7C513B
®
Functional description
The AS7C513B is a high performance CMOS 524,288-bit Static Random Access Memory (SRAM) device organized as 32,768 words × 16
bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for
high performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems.
When CE is high, the device enters standby mode. If inputs are still toggling, the device consumes ISB power. If the bus is static, then the full
standby power is reached (ISB1). The AS7C513B is guaranteed not to exceed 55mW power consumption under nominal full standby
conditions.
A write cycle is accomplished by asserting write enable (WE), (UB) and/or (LB), and chip enable (CE). Data on the input pins I/O0 - I/O7,
and/or I/O8 – I/O15, is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices
should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), (UB) and (LB), and chip enable (CE), with write enable (WE) high. The chips
drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is
active, or (UB) and (LB), output drivers stay in high-impedance mode.
The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0 – I/O7, and UB controls the higher bits, I/O8 – I/O15.
All chip inputs and outputs are TTL-compatible. The AS7C513B is packaged in common industry standard packages.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Voltage on VCC relative to GND
Vt1
–0.50
+7.0
V
Voltage on any pin relative to GND
Vt2
–0.50
VCC +0.50
V
Power dissipation
PD
–
Storage temperature (plastic)
Tstg
–65
Ambient temperature with VCC applied
Tbias
–55
1.0
W
+150
oC
+125
oC
DC current into outputs (low)
IOUT
–
20
mA
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
WE
OE
LB
H
X
X
X
L
H
L
L
L
H
L
H
L
H
L
L
L
L
X
L
L
L
X
L
L
L
X
H
L
H
H
X
L
X
X
H
Key: X = Don’t care; L = Low; H = High
UB
I/O0–I/O7 I/O8–I/O15
Mode
X
High Z
High Z
Standby (ISB, ISBI)
H
DOUT
High Z
Read I/O0–I/O7 (ICC)
L
High Z
DOUT
Read I/O8–I/O15 (ICC)
L
DOUT
DOUT
Read I/O0–I/O15 (ICC)
L
DIN
DIN
Write I/O0–I/O15 (ICC)
H
DIN
High Z
Write I/O0–I/O7 (ICC)
L
High Z
DIN
Write I/O8–I/O15 (ICC)
X
H
High Z
High Z
Output disable (ICC)
3/26/04, v.1.3
Alliance Semiconductor
P. 2 of 9
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