AT24C04BN-SP25-T データシートの表示（PDF） - Atmel Corporation

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AT24C04BN-SP25-T

Two-wire Automotive Temperature Serial EEPROM 1K (128 x 8) 2K (256 x 8) 4K (512 x 8) 8K (1024 x 8)

Atmel Corporation 

AT24C01B/02B/04B/08B

9. Device Addressing

The 1K/2K/4K/8K EEPROM device requires an 8-bit device address word following a start con-

dition to enable the chip for a read or write operation (see Figure 11-1 on page 10).

The device address word consists of a mandatory “1”, “0” sequence for the first four most signif-

icant bits as shown. This is common to all the Serial EEPROM devices.

The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM. These 3 bits

must compare to their corresponding hardwired input pins.

The 4K EEPROM only uses the A2 and A1 device address bits with the A0 bit being a memory

address bit (P0) (see Figure 11-1 on page 10). The two device address bits must compare to

their corresponding hardwired input pins. The A0 pin is no connect.

The 8K EEPROM only uses the A2 device address bit with the next two bits (P9, P0) being for

memory page addressing (See Figure 11-1 on page 10). The A2 bit must compare to its corre-

sponding hardwired input pin. The A1 and A0 pins are no connect.

The eighth bit of the device address is the read/write operation select bit. A read operation is ini-

tiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made,

the chip will return to a standby state.

10. Write Operations

BYTE WRITE: A write operation requires an 8-bit data word address following the device

address word and acknowledgment. Upon receipt of this address, the EEPROM will again

respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data

word, the EEPROM will output a “0” and the addressing device, such as a microcontroller, must

terminate the write sequence with a stop condition. At this time the EEPROM enters an internally

timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle

and the EEPROM will not respond until the write is complete (see Figure 11-2 on page 11).

PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write. The 4K/8K devices are

capable of 16-byte page writes.

A page write is initiated the same as a byte write, but the microcontroller does not send a stop

condition after the first data word is clocked in. Instead, after the EEPROM acknowledges

receipt of the first data word, the microcontroller can transmit up to seven (1K/2K) or fifteen (4K/

8K) more data words. The EEPROM will respond with a “0” after each data word received. The

microcontroller must terminate the page write sequence with a stop condition (see Figure 11-3

on page 11).

The data word address lower three (1K/2K) or four (4K/8K) bits are internally incremented fol-

lowing the receipt of each data word. The higher data word address bits are not incremented,

retaining the memory page row location. When the word address, internally generated, reaches

the page boundary, the following byte is placed at the beginning of the same page. If more than

eight (1K/2K) or sixteen (4K/8K) data words are transmitted to the EEPROM, the data word

address will “roll over” and previous data will be overwritten.

ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the

EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a

start condition followed by the device address word. The read/write bit is representative of the

9

8517C–SEEPR–01/09

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