AT24C04A-10TQ-2.7 データシートの表示（PDF） - Atmel Corporation
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AT24C04A-10TQ-2.7 Datasheet PDF : 20 Pages
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Figure 8. Byte Write
S
W
T
R
A
I
R
T
DEVICE
ADDRESS
T
E
WORD ADDRESS
DATA
S
T
O
P
SDA LINE
M
LRA M
LA
A
S
S/C S
SC
C
B
BW K B
BK
K
PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K, 8K,
and 16K devices are capable of 16-byte page writes.
A page write is initiated the same as a byte write, but the microcontroller does not send
a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to seven
(2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a “0”
after each data word received. The microcontroller must terminate the page write
sequence with a stop condition, as shown in Figure 9.
Figure 9. Page Write
S
T
A
R
T
DEVICE
ADDRESS
W
R
I
T
E WORD ADDRESS (n)
DATA (n)
DATA (n + 1)
S
T
O
DATA (n + x)
P
SDA LINE
M
LR A
A
A
A
A
S
S/ C
C
C
C
C
B
BW K
K
K
K
K
The data word address lower three (2K) or four (4K, 8K, 16K) bits are internally incre-
mented following the receipt of each data word. The higher data word address bits are
not incremented, retaining the memory page row location. When the word address,
internally generated, reaches the page boundary, the following byte is placed at the
beginning of the same page. If more than eight (2K) or sixteen (4K, 8K, 16K) data words
are transmitted to the EEPROM, the data word address will “roll over” and previous data
will be overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
ing a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a “0” allowing the read or write sequence to continue.
10 AT24C02A/04A/08A/16A
5083A–SEEPR–9/04
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