AT24C128B(2007) データシートの表示（PDF） - Atmel Corporation

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AT24C128B
(Rev.:2007)

Two-wire Serial EEPROM

Atmel Corporation 

AT24C128B [Preliminary]

SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire

part can be protocol reset by following these steps: (a) Create a start bit condition, (b) clock 9

cycles, (c) create another start bit followed by stop bit condition as shown below. The device is

ready for next communication after above steps have been completed.

Start Bit

Dummy Clock Cycles

Start Bit

SCL

1

2

3

8

9

Stop Bit

SDA

Figure 4. Bus Timing

Figure 5. Write Cycle Timing

SCL

SDA

8th BIT

WORDn

ACK

STOP

CONDITION

twr(1)

START

CONDITION

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end

of the internal clear/write cycle.

7

5208A–SEEPR–1/07

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