AT24C128B-TH-T データシートの表示（PDF） - Atmel Corporation

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AT24C128B-TH-T

Two-wire Serial EEPROM

Atmel Corporation 

AT24C128B

cycles, (c) create another start bit followed by stop bit condition as shown below. The device is

ready for next communication after above steps have been completed.

Figure 6-3. Software Reset

Start bit

Dummy Clock Cycles

Start bit

Stop bit

SCL

1

2

3

8

9

SDA

Figure 6-4. Bus Timing

SCL

SDA IN

tSU.STA

SDA OUT

Figure 6-5. Write Cycle Timing

SCL

tF

tLOW

tHD.STA

tHIGH

tHD.DAT

tLOW

tSU.DAT

tAA

tDH

tR

tSU.STO

tBUF

SDA

8th BIT

ACK

WORDn

STOP

CONDITION

(1)

twr

START

CONDITION

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

7

5296A–SEEPR–1/08

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