AT24C01ASC-09AT データシートの表示（PDF） - Atmel Corporation
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AT24C01ASC-09AT
Atmel Corporation
AT24C01ASC-09AT Datasheet PDF : 14 Pages
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AC Characteristics (Continued)
Applicable over recommended operating range from TA = 0°C to +70°C, VCC = +2.7V to +5.5V, CL = 1 TTL Gate and 100
pF (unless otherwise noted).
2.7-volt
5.0-volt
Symbol
Parameter
Min
Max
Min
Max
Units
tF
tSU.STO
tDH
tWR
Endurance(1)
Inputs Fall Time(1)
Stop Setup Time
Data Out Hold Time
Write Cycle Time
5.0V, 25°C, Page Mode
Note: 1. This parameter is characterized and is not 100% tested.
300
300
ns
4.7
0.6
µs
100
50
ns
10
10
ms
100K
100K
Write
Cycles
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is nor-
mally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as
defined below.
START CONDITION: A high-to-low transition of SDA with
SCL high is a start condition that must precede any other
command (refer to Start and Stop Definition timing dia-
gram).
STOP CONDITION: A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
Stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are
serially transmitted to and from the EEPROM in 8-bit
words. Each word requires the receiver to acknowledge
that it has received a valid command or data byte. During
the transmission of commands from the host to the
EEPROM, the EEPROM will send a zero to the host to
acknowledge that it has received a valid command byte.
This occurs on the ninth clock cycle of the command byte.
During read operations, the host will send a zero to the
EEPROM to acknowledge that it has received a valid data
byte and that it requests the next sequential data byte to be
transmitted during the subsequent eight clock cycles. This
occurs on the ninth clock cycle of the data byte. If the host
does not transmit this acknowledge bit, the EEPROM will
disable the Read operation and return to standby mode.
STANDBY MODE: The AT24C01ASC/02SC/04SC/
08SC/16SC features a low-power standby mode that is
enabled: (a) upon power-up and (b) after the receipt of the
STOP bit and the completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow-
ing these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition as SDA is high.
4 AT24C01ASC/02SC/04SC/08SC/16SC
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