74VHC138MTR(2004) データシートの表示（PDF） - STMicroelectronics

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74VHC138MTR
(Rev.:2004)

3 TO 8 LINE DECODER (INVERTING)

STMicroelectronics 

74VHC138

3 TO 8 LINE DECODER (INVERTING)

s HIGH SPEED: tPD = 5.7ns (TYP.) at VCC = 5V

s LOW POWER DISSIPATION:

ICC = 4 µA (MAX.) at TA=25°C

s HIGH NOISE IMMUNITY:

VNIH = VNIL = 28% VCC (MIN.)

s POWER DOWN PROTECTION ON INPUTS

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 8 mA (MIN)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 5.5V

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 138

s IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74VHC138 is an advanced high-speed

CMOS 3 TO 8 LINE DECODER (INVERTING)

fabricated with sub-micron silicon gate and

double-layer metal wiring C2MOS technology.

If the device is enabled, 3 binary select (A, B, and

C) determine which one of the outputs will go low.

If enable input G1 is held low or either G2A or G2B

is held high, the decoding function is inhibited and

all the 8 outputs go to high.

SOP

TSSOP

Table 1: Order Codes

PACKAGE

SOP

TSSOP

T&R

74VHC138MTR

74VHC138TTR

Tree enable inputs are provided to ease cascade

connection and application of address decoders

for memory systems.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

Figure 1: Pin Connection And IEC Logic Symbols

November 2004

Rev. 4

1/12

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