AT24C16B(2006) データシートの表示（PDF） - Atmel Corporation

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AT24C16B
(Rev.:2006)

Two-wire Serial EEPROM

Atmel Corporation 

Device

Addressing

Write

Operations

Read

Operations

5175A–SEEPR–09/06

AT24C16B Preliminary

The 16K EEPROM device requires an 8-bit device address word following a start condition to

enable the chip for a read or write operation (refer to Figure 7).

The device address word consists of a mandatory one, zero sequence for the first four most

significant bits as shown. This is common to all the EEPROM devices.

The next 3 bits used for memory page addressing and are the most significant bits of the data

word address which follows.

The eighth bit of the device address is the read/write operation select bit. A read operation is

initiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a compare is not

made, the chip will return to a standby state.

BYTE WRITE: A write operation requires an 8-bit data word address following the device

address word and acknowledgment. Upon receipt of this address, the EEPROM will again

respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit

data word, the EEPROM will output a zero and the addressing device, such as a microcontrol-

ler, must terminate the write sequence with a stop condition. At this time the EEPROM enters

an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during

this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on

page 11).

PAGE WRITE: The 16K EEPROM is capable of an 16-byte page write.

A page write is initiated the same as a byte write, but the microcontroller does not send a stop

condition after the first data word is clocked in. Instead, after the EEPROM acknowledges

receipt of the first data word, the microcontroller can transmit up to fifteen data words. The

EEPROM will respond with a zero after each data word received. The microcontroller must ter-

minate the page write sequence with a stop condition (see Figure 9 on page 11).

The data word address lower three bits are internally incremented following the receipt of each

data word. The higher data word address bits are not incremented, retaining the memory page

row location. When the word address, internally generated, reaches the page boundary, the

following byte is placed at the beginning of the same page. If more than sixteen data words

are transmitted to the EEPROM, the data word address will “roll over” and previous data will

be overwritten.

ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the

EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a

start condition followed by the device address word. The read/write bit is representative of the

operation desired. Only if the internal write cycle has completed will the EEPROM respond

with a zero allowing the read or write sequence to continue.

Read operations are initiated the same way as write operations with the exception that the

read/write select bit in the device address word is set to one. There are three read operations:

current address read, random address read and sequential read.

CURRENT ADDRESS READ: The internal data word address counter maintains the last

address accessed during the last read or write operation, incremented by one. This address

stays valid between operations as long as the chip power is maintained. The address “roll

over” during read is from the last byte of the last memory page to the first byte of the first page.

The address “roll over” during write is from the last byte of the current page to the first byte of

the same page.

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