AT24C64B-W1.8-11(2007) データシートの表示（PDF） - Atmel Corporation

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AT24C64B-W1.8-11
(Rev.:2007)

2-Wire Serial EEPROM

Atmel Corporation 

AT24C64B

5. Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external

device. Data on the SDA pin may change only during SCL low time periods (refer to Data Valid-

ity timing diagram). Data changes during SCL high periods will indicate a start or stop condition

as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which

must precede any other command (refer to Start and Stop Definition timing diagram).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a

read sequence, the stop command will place the EEPROM in a standby power mode (refer to

Start and Stop Definition timing diagram).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the

EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-

edge that it has received each word.

STANDBY MODE: The AT24C64B features a low power standby mode which is enabled: a)

upon power-up and b) after the receipt of the Stop bit and the completion of any internal

operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part

can be reset by following these steps:

(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create

a start condition as SDA is high.

5

3350E–SEEPR–9/07

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