AT24C64D データシートの表示（PDF） - Atmel Corporation

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AT24C64D

2-Wire Serial Electrically Erasable and Programmable Read-only Memory

Atmel Corporation 

Atmel AT24C32D/64D

2. Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and

negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may

be wire-ORed with any number of other open-drain or open collector devices.

DEVICE/ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired or left

not connected for hardware compatibility with other Atmel® AT24CXX devices. When the pins are hardwired, as

many as eight 32K/64K devices may be addressed on a single bus system (device addressing is discussed in

detail under the Device Addressing section). If the pins are left floating, the A2, A1 and A0 pins will be internally

pulled down to GND if the capacitive coupling to the circuit board VCC plane is <3pF. If coupling is >3pF, Atmel

recommends connecting the address pins to GND.

WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When

WP is connected high to VCC, all write operations to the memory are inhibited. If the pin is left floating, the WP pin

will be internally pulled down to GND if the capacitive coupling to the circuit board VCC plane is <3pF. If coupling is

>3pF, Atmel recommends connecting the pin to GND.

3

8717B–SEEPR–6/10

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