AT24C512B-10PU-1.8 データシートの表示（PDF） - Atmel Corporation

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AT24C512B-10PU-1.8

Two-wire Serial EEPROM 512K (65,536 x 8)

Atmel Corporation 

AT24C512B [Preliminary]

Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each

EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is

open-drain driven and may be wire-ORed with any number of other open-drain or open

collector devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device

address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other

AT24Cxx devices. When the pins are hardwired, as many as eight 512K devices may be

addressed on a single bus system. (Device addressing is discussed in detail under

“Device Addressing,” page 8.) A device is selected when a corresponding hardware and

software match is true. If these pins are left floating, the A2, A1, and A0 pins will be

internally pulled down to GND. However, due to capacitive coupling that may appear

during customer applications, Atmel recommends always connecting the address pins

to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less.

WRITE PROTECT (WP): The write protect input, when connected to GND, allows nor-

mal write operations. When WP is connected directly to Vcc, all write operations to the

memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down

to GND. However, due to capacitive coupling that may appear during customer applica-

tions, Atmel recommends always connecting the WP pins to a known state. When using

a pull-up resistor, Atmel recommends using 10kΩ or less.

Memory Organization AT24C512B, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages

of 128-bytes each. Random word addressing requires a 16-bit data word address.

3

5112A–SEEPR–8/05

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