AT25080B データシートの表示（PDF） - Atmel Corporation
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AT25080B Datasheet PDF : 22 Pages
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Table 2-1. Instruction Set for the AT25080B/160B
Instruction Name
Instruction Format
Operation
WRSR
0000 X001
Write Status Register
READ
0000 X011
Read Data from Memory Array
WRITE
0000 X010
Write Data to Memory Array
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is
applied. All programming instructions must therefore be preceded by a Write Enable instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable
instruction disables all programming modes. The WRDI instruction is independent of the status
of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to
the status register. The READY/BUSY and Write Enable status of the device can be determined
by the RDSR instruction. Similarly, the Block Write Protection Bits indicate the extent of protec-
tion employed. These bits are set by using the WRSR instruction.
Table 2-2.
Bit 7
WPEN
Status Register Format
Bit 6
Bit 5
Bit 4
X
X
X
Bit 3
BP1
Bit 2
BP0
Bit 1
WEN
Bit 0
RDY
Table 2-3. Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = “0” (RDY) indicates the device is READY. Bit 0 = “1” indicates the write cycle
is in progress.
Bit 1 (WEN)
Bit 1= “0” indicates the device is not WRITE ENABLED. Bit 1 = “1” indicates the
device is write enabled.
Bit 2 (BP0)
See Table 2-4 on page 9.
Bit 3 (BP1)
See Table 2-4 on page 9.
Bits 4–6 are “0”s when device is not in an internal write cycle.
Bit 7 (WPEN)
See Table 2-5 on page 9.
Bits 0–7 are “1”s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of
four levels of protection. The AT25080B/160B is divided into four array segments. One-quarter,
one-half, or all of the memory segments can be protected. Any of the data within any selected
segment will therefore be read only. The block write protection levels and corresponding status
register control bits are shown in Table 2-4.
The three bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and
functions as the regular memory cells (e.g., WREN, tWC, RDSR).
8 AT25080B/160B [Preliminary]
5228B–SEEPR–7/08
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