AT24C01A-W2.7-11 データシートの表示（PDF） - Atmel Corporation

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AT24C01A-W2.7-11

Two-wire Serial EEPROM 1K (128 x 8) 2K (256 x 8) 4K (512 x 8) 8K (1024 x 8) 16K (2048 x 8)

Atmel Corporation 

Bus Timing

Figure 2. SCL: Serial Clock, SDA: Serial Data I/O

AT24C01A/02/04/08A/16A

Write Cycle Timing

Figure 3. SCL: Serial Clock, SDA: Serial Data I/O

SCL

SDA

8th BIT

WORDn

ACK

STOP

CONDITION

twr(1)

START

CONDITION

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

Figure 4. Data Validity

7

0180V–SEEPR–8/05

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