NX26F640C データシートの表示（PDF） - NexFlash -> Winbond Electronics

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NX26F640C

64M-BIT SERIAL FLASH MEMORY WITH 2-PIN NXS2 INTERFACE

NexFlash -> Winbond Electronics 

NX26F640C

Table 2. Write Protect Range Sector Selection

Write Protect

Range Config. Bits

WR3 WR2 WR1 WR0

00 00

00 01

00 10

00 11

01 00

01 01

01 10

01 11

10 00

10 01

10 10

10 11

11 00

11 01

11 10

11 11

Write Protected Sectors (Hex)

WD=0

WD=1

None

None

0000-003F 3FC0-3FFF

0000-007F 3F80-3FFF

0000-00BF 3F40-3FFF

0000-00FF 3F00-3FFF

0000-013F 3EC0-3FFF

0000-017F 3E80-3FFF

0000-01BF 3E40-3FFF

0000-01FF 3E00-3FFF

0000-023F 3DC0-3FFF

0000-027F 3D80-3FFF

0000-02BF 3D40-3FFF

0000-02FF 3D00-3FFF

0000-033F 3CC0-3FFF

0000-037F 3C80-3FFF

ALL

ALL

Status Register Bit Descriptions

The status register provides status of the Flash array’s

Ready/Busy condition (R/B), transfers between the SRAM

and program buffer (TR0 and TR1), Write-Enable/Disable

(WE), Compare Not Equal (CNE), Power Detect (PD) and

Data Integrity status (DI0 and DI1). The register can be

read using the Read Status Register command

(Figure 7).

Ready/Busy Status, BUSY

The BUSY status bit is located at bit ST[15] of the status

register. Testing the BUSY bit is one of several ways to

check Ready/Busy status of the array. At power-up the

BUSY bit is reset to 0.

BUSY=1 The device is busy programming.

BUSY=0 The deivce is ready for further use.

SRAM Transfer, TR0 and TR1

The TR status bits are located at bit ST[13] and ST[14] of

the status register. The bits provide status during the

Transfer Sector to SRAM, Transfer SRAM to SRAM, and

Refresh Sector commands. An active state 1 indicates the

SRAM Array is not available for use. The device will also

indicate a BUSY state while the TR bits are active. Upon

power up the TR bits reset to 0.

TR=1 Transfer, or Refresh in Process.

TR=0 Transfer, or Refresh not in Process.

10

NexFlash Technologies, Inc.

PRELIMINARY NXSF020D-0902

09/05/02 ©

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