NX26F640C-3T データシートの表示（PDF） - NexFlash -> Winbond Electronics
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NX26F640C-3T Datasheet PDF : 23 Pages
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NX26F640C
SCK
SIO
DA[7:0]
Device Address
C[7:0]
Command
B[15:0]
Byte Address
0 0 0 0 0 DA2 DA1 DA0 C7 C6 C5 C4 C3 C2 C1 C0 0 0 0 0 0 0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
71H or 73H
SIO is Driven by NX26F640C
8 Clocks
SCK
SIO
0 0 0 0 0 0 00
1st Byte of Data
2nd Byte of Data
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D4 D5 D3 D2 D1 D0
SCK
SIO
n-Bytes of Data
Last Byte of Data
D7 D6 D5 D4 D3 D2 D1 D0
Figure 12. Read from SRAM Command Sequence
Idle
High-Z
SERIAL FLASH SECTOR AND SRAM READ
COMMANDS
Transfer Sector to SRAM (5CH and 5DH)
The Transfer Sector to SRAM command transfers the con-
tents of a specified 522-byte sector directly to the SRAM.
Writing to a sector is accomplished by first bringing CS
low and shifting in the Transfer Sector to SRAM com-
mand (53H and 5DH) followed by a 16-bit
“sector-address” field. Although the sector-address field
is 16-bits, only bits S[13:0] are used. The uppermost
sector address bits are not used but must be clocked
in (use 0 data). Following the sector address, a 32-bit
“0” field is clocked into the device. The transfer opera-
tion will start and the Busy and TR bit in the status
register will be set. The Status Register bits ST[15:0] are
then provided on the SO output every 16 clocks. This fea-
ture allows the Busy and TR bit in the status register to be
checked without sending a separate Status Register com-
mand. When the transfer operation is complete the Busy
and TR bits in the status register will be cleared and the
Data Integrity bits DI0 and DI1 can be checked to confirm
that data is valid.
Read SRAM (71H and 73H)
The Read SRAM command (71H and 73H) provides
access to the 522-Byte SRAM independent of any Flash
memory array operations. The TR bit in the status register
should be checked first if Transfer Sector to SRAM or
NexFlash Technologies, Inc.
15
PRELIMINARY NXSF020D-0902
09/05/02 ©
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