NX26F640C-3T データシートの表示（PDF） - NexFlash -> Winbond Electronics

部品番号

コンポーネント説明

メーカー

NX26F640C-3T

64M-BIT SERIAL FLASH MEMORY WITH 2-PIN NXS2 INTERFACE

NexFlash -> Winbond Electronics 

NX26F640C

The Write Configuration Register command sequence

starts with the command byte (8AH) followed by a 16-bit

field that specifies configuration register bit settings.

Although the field is 16-bits long, only bits CF[7:0] are

used. All other upper bits are reserved and must be

clocked using 0 for data. After an additional 16 control

clocks using 0 for data, the command can be completed by

asserting CS high. The device will become busy for a short

time (tWP) while the non-volatile memory cells of the

configuration register are programmed.

Read Status Register (84H)

The Read Status Register command provides access to

the status register and its status flags for Ready/Busy

(R/B), SRAM buffer transfer operations (TR0 and TR1),

Write Enable/Disable (WE), Power Detect and Data Integ-

rity bits (Figure 6). An 16-bit Status field ST[16:0] provides

the contents of the Status Register.

Clear Power Detection Bit (09H)

The Reset Power Detection Bit command (09H) can be

used to force the Power Detect Status bit in the status

register to a 0 state. (see Set Power Detection Bit com-

mand (03H).

Set Power Detection Bit (03H)

The Set Power Detection Bit command (03H) can be used

to detect if power has been removed from the device. The

command works in conjunction with the Power Detect (PD)

status bit. Upon power up the PD bit is cleared to 0. The PD

bit can be set to a 1 using the Set Power Detection Bit

command. Once set, if a power down condition occurs

(Vcc voltage < 2V) the PD bit will reset to 0. This function

is especially useful for applications using NexFlash Serial

Flash Modules or other removable media.

18

NexFlash Technologies, Inc.

PRELIMINARY NXSF020D-0902

09/05/02 ©

Share Link: