5962-8863401ZX データシートの表示（PDF） - Atmel Corporation

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5962-8863401ZX

256 (32K x 8) High-speed Parallel EEPROM

Atmel Corporation 

Features

• Fast Read Access Time – 70 ns

• Automatic Page Write Operation

– Internal Address and Data Latches for 64 Bytes

– Internal Control Timer

• Fast Write Cycle Times

– Page Write Cycle Time: 3 ms or 10 ms Maximum

– 1 to 64-byte Page Write Operation

• Low Power Dissipation

– 80 mA Active Current

– 3 mA Standby Current

• Hardware and Software Data Protection

• DATA Polling for End of Write Detection

• High Reliability CMOS Technology

– Endurance: 104 or 105 Cycles

– Data Retention: 10 Years

• Single 5V ± 10% Supply

• CMOS and TTL Compatible Inputs and Outputs

• JEDEC Approved Byte-wide Pinout

• Full Military, Commercial, and Industrial Temperature Ranges

• Green (Pb/Halide-free) Packaging Option

256 (32K x 8)

High-speed

Parallel

EEPROM

AT28HC256

1. Description

The AT28HC256 is a high-performance electrically erasable and programmable read-

only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufac-

tured with Atmel’s advanced nonvolatile CMOS technology, the AT28HC256 offers

access times to 70 ns with power dissipation of just 440 mW. When the AT28HC256

is deselected, the standby current is less than 5 mA.

The AT28HC256 is accessed like a Static RAM for the read or write cycle without the

need for external components. The device contains a 64-byte page register to allow

writing of up to 64 bytes simultaneously. During a write cycle, the address and 1 to 64

bytes of data are internally latched, freeing the addresses and data bus for other oper-

ations. Following the initiation of a write cycle, the device will automatically write the

latched data using an internal control timer. The end of a write cycle can be detected

by DATA Polling of I/O7. Once the end of a write cycle has been detected a new

access for a read or write can begin.

Atmel’s 28HC256 has additional features to ensure high quality and manufacturability.

The device utilizes internal error correction for extended endurance and improved

data retention characteristics. An optional software data protection mechanism is

available to guard against inadvertent writes. The device also includes an extra

64 bytes of EEPROM for device identification or tracking.

0007J–PEEPR–04/05

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