AT40K10-2DQI データシートの表示（PDF） - Atmel Corporation
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AT40K10-2DQI Datasheet PDF : 67 Pages
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Cell Connections
Figure 4(a) depicts direct connections between a cell and its eight nearest neighbors.
Figure 4(b) shows the connections between a cell and five horizontal local buses (1 per
busing plane) and five vertical local buses (1 per busing plane).
Figure 4. Cell Connections
CELL
CELL
CELL
Plane
5
Plane
4
Plane
3
Plane
2
Plane
1
Horizontal
Busing Plane
WXYZL
CELL
CELL
CELL
W
X
Y
Z
CELL
L
Diagonal
Direct Connect
Vertical
Busing Plane
CELL
CELL
CELL
Orthogonal
Direct Connect
The Cell
(a) Cell-to-cell Connections
(b) Cell-to-bus Connections
Figure 5 depicts the AT40K/AT40KLV cell. Configuration bits for separate muxes and
pass gates are independent. All permutations of programmable muxes and pass gates
are legal. Vn (V1 - V5) is connected to the vertical local bus in plane n. Hn (H1 - H5) is
connected to the horizontal local bus in plane n. A local/local turn in plane n is achieved
by turning on the two pass gates connected to Vn and Hn. Pass gates are opened to let
signals into the cell from a local bus or to drive a signal out onto a local bus. Signals
coming into the logic cell on one local bus plane can be switched onto another plane by
opening two of the pass gates. This allows bus signals to switch planes to achieve
greater route ability. Up to five simultaneous local/local turns are possible.
The AT40K/AT40KLV FPGA core cell is a highly configurable logic block based around
two 3-input LUTs (8 x 1 ROM), which can be combined to produce one 4-input LUT.
This means that any core cell can implement two functions of 3 inputs or one function of
4 inputs. There is a Set/Reset D flip-flop in every cell, the output of which may be tri-
stated and fed back internally within the core cell. There is also a 2-to-1 multiplexer in
every cell, and an upstream AND gate in the “front end” of the cell. This AND gate is an
important feature in the implementation of efficient array multipliers.
With this functionality in each core cell, the core cell can be configured in several
“modes”. The core cell flexibility makes the AT40K/AT40KLV architecture well suited to
most digital design application areas, see Figure 6.
8 AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
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