AT88SC0808C-SI データシートの表示（PDF） - Atmel Corporation

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AT88SC0808C-SI

8 x 128 x 8 CryptoMemory™

Atmel Corporation 

AT88SC0808C

Protocol Selection

Asynchronous

T = 0 Protocol

Synchronous

Two-wire Protocol

The AT88SC0808C is compatible with two different communication protocols: asynchro-

nous T = 0 as defined by ISO 7816-3 or synchronous two-wire protocol. The power-up

sequence determines which of the two protocols will be used.

The power-up sequence complies with ISO 7816-3 for a cold reset.

• VCC goes high; RST, I/O-SDA and CLK-SCL are low.

• Set I/O-SDA in receive mode.

• Provide a clock signal to CLK-SCL.

• RST goes high after 400 clock cycles.

The device will respond with a 64-bit ATR code, including historical bytes to indicate the

memory density within the CryptoMemory family. Once the asynchronous mode has

been selected, it is not possible to switch to the synchronous mode without powering off

the device.

Figure 2. Asynchronous T = 0 Protocol

Vcc

I/O-SDA

ATR

RST

CLK-SCL

The synchronous mode is the default after powering up VCC due to the internal pull-up

on RST.

• Power-up VCC, RST goes high also.

• After stable VCC, CLK-SCL and I/O-SDA may be driven.

Figure 3. Synchronous Two-wire Protocol

Vcc

I/O-SDA

RST

CLK-SCL

1 234

Note: Four clock pulses must be sent before the first command is issued.

5

2024BS–SMEM–10/02

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