ATA6622(2008) データシートの表示（PDF） - Atmel Corporation

部品番号

コンポーネント説明

メーカー

ATA6622
(Rev.:2008)

LIN Bus Transceiver with 3.3V (5V) Regulator and Watchdog

Atmel Corporation 

ATA6622/ATA6624/ATA6626

6. Watchdog

The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge)

input within a time window of Twd. The trigger signal must exceed a minimum time

ttrigmin > 200 ns. If a triggering signal is not received, a reset signal will be generated at output

NRES. The timing basis of the watchdog is provided by the internal oscillator. Its time period,

Tosc, is adjustable via the external resistor Rwd_osc (34 kΩ to 120 kΩ).

During Silent or Sleep Mode the watchdog is switched off to reduce current consumption.

The minimum time for the first watchdog pulse is required after the undervoltage reset at NRES

disappears. It is defined as lead time td. After wake up from Sleep or Silent Mode, the lead time

td starts with the negative edge of the RXD output.

6.1 Typical Timing Sequence with RWD_OSC = 51 kΩ

The trigger signal Twd is adjustable between 20 ms and 64 ms using the external resistor

RWD_OSC.

For example, with an external resistor of RWD_OSC = 51 kΩ ±1%, the typical parameters of the

watchdog are as follows:

tosc = 0.405 × RWD_OSC – 0.0004 × (RWD_OSC)2 (RWD_OSC in kΩ; tosc in µs)

tOSC = 19.6 µs due to 51 kΩ

td = 7895 × 19.6 µs = 155 ms

t1 = 1053 × 19.6 µs = 20.6 ms

t2 = 1105 × 19.6 µs = 21.6 ms

tnres = constant = 4 ms

After ramping up the battery voltage, the 3.3V/5V regulator is switched on. The reset output

NRES stays low for the time treset (typically 4 ms), then it switches to high, and the watchdog

waits for the trigger sequence from the microcontroller. The lead time, td, follows the reset and is

td = 155 ms. In this time, the first watchdog pulse from the microcontroller is required. If the trig-

ger pulse NTRIG occurs during this time, the time t1 starts immediately. If no trigger signal

occurs during the time td, a watchdog reset with tNRES = 4 ms will reset the microcontroller after

td = 155 ms. The times t1 and t2 have a fixed relationship between each other. A triggering signal

from the microcontroller is anticipated within the time frame of t2 = 21.6 ms. To avoid false trig-

gering from glitches, the trigger pulse must be longer than tTRIG,min > 200 ns. This slope serves to

restart the watchdog sequence. If the triggering signal fails in this open window t2, the NRES

output will be drawn to ground. A triggering signal during the closed window t1 immediately

switches NRES to low.

15

4986F–AUTO–07/08

Share Link: