ATA6630 データシートの表示（PDF） - Atmel Corporation

部品番号

コンポーネント説明

メーカー

ATA6630

LIN Bus Transceiver with 3.3V (5V) Regulator and Watchdog

Atmel Corporation 

6. Watchdog

The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge) input within a time window

of Twd. The trigger signal must exceed a minimum time ttrigmin > 200ns. If a triggering signal is not received, a reset signal will

be generated at output NRES. The timing basis of the watchdog is provided by the internal oscillator. Its time period, Tosc, is

adjustable via the external resistor Rwd_osc (34kΩ to 120kΩ).

During Silent or Sleep Mode the watchdog is switched off to reduce current consumption.

The minimum time for the first watchdog pulse is required after the undervoltage reset at NRES disappears. It is defined as

lead time td. After wake up from Sleep or Silent Mode, the lead time td starts with the negative edge of the RXD output.

6.1 Typical Timing Sequence with RWD_OSC = 51kΩ

The trigger signal Twd is adjustable between 20ms and 64ms using the external resistor RWD_OSC.

For example, with an external resistor of RWD_OSC = 51kΩ ±1%, the typical parameters of the watchdog are as follows:

tosc = 0.405 × RWD_OSC – 0.0004 × (RWD_OSC)2 (RWD_OSC in kΩ ; tosc in µs)

tOSC = 19.6µs due to 51kΩ

td = 7895 × 19.6µs = 155ms

t1 = 1053 × 19.6µs = 20.6ms

t2 = 1105 × 19.6µs = 21.6ms

tnres = constant = 4ms

After ramping up the battery voltage, the 5V regulator is switched on. The reset output NRES stays low for the time treset

(typically 4ms), then it switches to high, and the watchdog waits for the trigger sequence from the microcontroller. The lead

time, td, follows the reset and is td = 155ms. In this time, the first watchdog pulse from the microcontroller is required. If the

trigger pulse NTRIG occurs during this time, the time t1 starts immediately. If no trigger signal occurs during the time td, a

watchdog reset with tNRES = 4 ms will reset the microcontroller after td = 155ms. The times t1 and t2 have a fixed relationship.

A triggering signal from the microcontroller is anticipated within the time frame of t2 = 21.6ms. To avoid false triggering from

glitches, the trigger pulse must be longer than tTRIG,min > 200ns. This slope serves to restart the watchdog sequence. If the

triggering signal fails in this open window t2, the NRES output will be drawn to ground. A triggering signal during the closed

window t1 immediately switches NRES to low.

Figure 6-1. Timing Sequence with RWD_OSC = 51kΩ

VCC

3.3V/5V

NRES

Undervoltage Reset

treset = 4ms

Watchdog Reset

tnres = 4ms

td = 155ms

t1

t2

t1 = 20.6ms

t2 = 21ms

twd

NTRIG

ttrig > 200ns

ATA6628/ATA6630 [DATASHEET]

19

9117I–AUTO–10/14

Share Link: