ATF1502ASV(2004) データシートの表示（PDF） - Atmel Corporation

部品番号

コンポーネント説明

メーカー

ATF1502ASV
(Rev.:2004)

High performance EEPROM CPLD

Atmel Corporation 

Input Diagram

VCC

I/O Diagram

INPUT

OE

DATA

ESD

PROTECTION

CIRCUIT

100K

PROGRAMMABLE

OPTION

VCC

I/O

VCC

100K

PROGRAMMABLE

OPTION

Speed/Power

Management

The ATF1502ASV has several built-in speed and power management features.

To further reduce power, each ATF1502ASV macrocell has a reduced-power bit feature.

To reduce power consumption this feature may be actived (by changing the default

value of OFF to ON) for any or all macrocells.

The ATF1502ASV also has an optional power-down mode. In this mode, current drops

to below 15 mA. When the power-down option is selected, either PD1 or PD2 pins (or

both) can be used to power down the part. The power-down option is selected in the

design source file. When enabled, the device goes into power-down when either PD1 or

PD2 is high. In the power-down mode, all internal logic signals are latched and held, as

are any enabled outputs.

All pin transitions are ignored until the PD pin is brought low. When the power-down fea-

ture is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However,

the pin’s macrocell may still be used to generate buried foldback and cascade logic

signals.

6 ATF1502ASV

1615H–PLD–2/04

Share Link: