ATF1516SE-10QC208 データシートの表示（PDF） - Atmel Corporation

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ATF1516SE-10QC208

ATF15xxSE Family Datasheet

Atmel Corporation 

Power-on Reset

Power Down of

Unused

Macrocells

Input Transition

Detection/

Automatic Power

Down

Reduced-Power

per Macrocell

Slew Rate Control

Pin Controlled

Power-down

The ATF15xx Family devices are designed with a power-on reset, a feature critical for state

machine initialization. At a point delayed slightly from VCC crossing VRST, all registers will be

initialized, and the state of each output will depend on the polarity of its buffer. However, due

to the asynchronous nature of reset and uncertainty of how VCC actually rises in the system,

the following conditions are required:

1. The VCC rise must be monotonic,

2. After reset occurs, all input and feedback setup times must be met before driving the

clock pin high, and,

3. The clock must remain stable during TD.

The ATF15xx Family has two options for the hysteresis about the reset level, VRST, Small and

Large. In applications where the supply voltage may drop below 4.0V, Atmel recommends that

during the fitting process users configure the device with the Power-on Reset hysteresis set to

Large to ensure a robust operating environment.

To conserve power, Atmel fitters automatically power down all unused macrocells.

The ATF15xxSEL versions provide automatic power-down to µA level stand-by power (the “L”

suffix indicates “Low” power) through Atmel’s patented Input Transition Detection (ITD) cir-

cuitry on Global Clocks, Inputs and I/O. These ITD circuits automatically put the device into a

low-power standby mode when no logic transitions are occurring. This reduces power con-

sumption during inactive periods, and so provides proportional power savings for most

applications running at system speeds below fCRITICAL (~5 MHz).

In clocked applications, where the device is operated at a frequency high enough to keep the

device from going into stand-by (above fCRITICAL), the device will perform at the faster speeds

given in the next faster speed column. These higher speeds can be achieved in combinatorial

designs as well, as long as once activated by an initial input transition, the device continues to

receive input transitions often enough to keep the device from going into standby mode again.

That is, the time between input transitions is less than 1/fCRITICAL.

To further reduce power, each ATF15xxSE Family macrocell has a reduced-power bit feature.

With this feature the designer can reduce power by 50% or more for logic that does not need

to operate at the maximum switching speed. The reduced-power bit may be activated by

changing the default OFF to ON for any or all macrocells. For macrocells in reduced-power

mode (reduced-power bit turned on), the reduced- power adder, tRPA, must be added to the

AC parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP. All power-down

AC characteristic parameters are computed from external input or I/O pins, with the reduced-

power bit turned on.

Each output also has individual slew rate control. This may be used to reduce system noise by

slowing down outputs that do not need to operate at maximum speed. Outputs default to slow

switching. The slew rate option is selected in the design source file.

All ATF15xx Family devices also have an optional pin-controlled power-down mode. When

activated, one or both of two pins, PD1 and PD2, can act as power-down pins. The device

goes into power-down when either PD1 or PD2 pins (or both) are high, and the device supply

current is reduced to less than 1 mA. Also, all internal logic signals are latched and held, as

are any enabled outputs. Therefore, all registered and combinatorial output data remain valid.

Any outputs that were in a high-Z state at the onset will remain at high-Z. Input and I/O hold

8 ATF15xxSE Family

2401D–PLD–09/02

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