ATR2406-DEV-KIT データシートの表示（PDF） - Atmel Corporation

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ATR2406-DEV-KIT

Low IF 2.4 GHz ISM Transceiver

Atmel Corporation 

GFCS Adjustment

ATR2406 [Preliminary]

Table 4. PLL Settings with the Main Counter Bits D5 - D6

MC (Main Counter)

D6

D5

SMC

0

0

86

0

1

87

1

0

88

1

1

89

Table 5. PLL Settings with the Swallow Counter Bits D0 - D4

SC (Swallow Counter)

D4

D3

D2

D1

D0

SSC

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

1

0

2

...

...

...

...

...

...

1

1

1

0

1

29

1

1

1

1

0

30

1

1

1

1

1

31

The Gaussian Filter Control Setting is used to compensate production tolerances by

tuning the modulation deviation in production to the nominal value of 400 kHz. These

bits are only relevant in TX mode.

Table 6. GFCS Adjustment with Bits D9 - D11

GFCS (Gaussian Filter Control Settings)

D11

D10

D9

GFCS

0

0

0

60%

0

0

1

70%

0

1

0

80%

0

1

1

90%

1

0

0

100%

1

0

1

110%

1

1

0

120%

1

1

1

130%

The VRAMP voltage is used to control the output power of an external power amplifier.

The voltage ramp is started with the TX_ON signal.

These bits are only relevant in TX mode.

11

4779F–ISM–09/04

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