ATTINY13-10SU データシートの表示（PDF） - Atmel Corporation

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ATTINY13-10SU

8-bit Microcontroller with 1K Bytes In-System Programmable Flash

Atmel Corporation 

ATtiny13

5. Memories

This section describes the different memories in the ATtiny13. The AVR architecture has two

main memory spaces, the Data memory and the Program memory space. In addition, the

ATtiny13 features an EEPROM Memory for data storage. All three memory spaces are linear

and regular.

5.1 In-System Reprogrammable Flash Program Memory

The ATtiny13 contains 1K byte On-chip In-System Reprogrammable Flash memory for program

storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 512 x 16.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny13 Pro-

gram Counter (PC) is nine bits wide, thus addressing the 512 Program memory locations.

“Memory Programming” on page 102 contains a detailed description on Flash data serial down-

loading using the SPI pins.

Constant tables can be allocated within the entire Program memory address space (see the

LPM – Load Program memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 12.

Figure 5-1.

Program Memory Map

Program Memory

0x0000

0x01FF

5.2 SRAM Data Memory

Figure 5-2 on page 16 shows how the ATtiny13 SRAM Memory is organized.

The lower 160 Data memory locations address both the Register File, the I/O memory and the

internal data SRAM. The first 32 locations address the Register File, the next 64 locations the

standard I/O memory, and the last 64 locations address the internal data SRAM.

The five different addressing modes for the Data memory cover: Direct, Indirect with Displace-

ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register

File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given

by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented.

15

2535I–AVR–05/08

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