ATTINY20 データシートの表示（PDF） - Atmel Corporation
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ATTINY20 Datasheet PDF : 219 Pages
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1.5 Pin Description
1.5.1 VCC
Supply voltage.
1.5.2 GND
Ground.
1.5.3
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not
running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 20-4 on page 170.
Shorter pulses are not guaranteed to generate a reset.
The reset pin can also be used as a (weak) I/O pin.
1.5.4
Port A (PA7:PA0)
Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have
symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally
pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition
becomes active, even if the clock is not running.
Port A has alternate functions as analog inputs for the ADC, analog comparator and pin change interrupt as described in
“Alternate Port Functions” on page 47.
1.5.5
Port B (PB3:PB0)
Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have
symmetrical drive characteristics with both high sink and source capability except PB3 which has the RESET capability.
To use pin PB3 as an I/O pin, instead of RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
The port also serves the functions of various special features of the ATtiny20, as listed on page 37.
ATtiny20 [DATASHEET]
4
Atmel-8235F-AVR-ATtiny20-Datasheet_09/2014
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