ATTINY20 データシートの表示（PDF） - Atmel Corporation
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ATTINY20 Datasheet PDF : 219 Pages
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Six of the 16 registers can be used as three 16-bit indirect address register pointers for data space addressing – enabling
efficient address calculations. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this
section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register
operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect
information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, capable of directly addressing the
whole address space. Most AVR instructions have a single 16-bit word format but 32-bit wide instructions also exist. The
actual instruction set varies, as some devices only implement a part of the instruction set.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is
effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the SRAM size and the
usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are
executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the four different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the
Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in
accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O
functions. The I/O memory can be accessed as the data space locations, 0x0000 - 0x003F.
4.2 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 16 general purpose working registers. Within a
single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are
executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some
implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and
fractional format. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 205 for a detailed
description.
4.3 Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional operations. Note that the Status
Register is updated after all ALU operations, as specified in document “AVR Instruction Set” and section “Instruction Set
Summary” on page 205. This will in many cases remove the need for using the dedicated compare instructions, resulting
in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an
interrupt. This must be handled by software.
4.4 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance
and flexibility, the following input/output schemes are supported by the Register File:
z One 8-bit output operand and one 8-bit result input
z Two 8-bit output operands and one 8-bit result input
z One 16-bit output operand and one 16-bit result input
Figure 4-2 below shows the structure of the 16 general purpose working registers in the CPU.
ATtiny20 [DATASHEET]
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Atmel-8235F-AVR-ATtiny20-Datasheet_09/2014
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