ATTINY22 データシートの表示（PDF） - Atmel Corporation
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ATTINY22 Datasheet PDF : 59 Pages
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Features
• Utilizes the AVR® RISC Architecture
• AVR - High-performance and Low-power RISC Architecture
– 118 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
• Data and Nonvolatile Program Memory
– 2K Bytes of In-System Programmable Flash
Endurance 1,000 Write/Erase Cycles
– 128 Bytes of internal SRAM
– 128 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In-System Programming
• Special Microcontroller Features
– Low-power Idle and Power Down Modes
– External and Internal Interrupt Sources
– Power-on Reset Circuit
– Selectable On-chip RC Oscillator
• Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
• Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.4 mA
– Idle Mode: 0.5 mA
– Power Down Mode: <1 µA
• I/O and Packages
– 5 Programmable I/O Lines
– 8-pin PDIP and SOIC
• Operating Voltages
– 2.7 - 6.0V (ATtiny22L)
– 4.0 - 6.0V (ATtiny22)
• Speed Grades
– 0 - 4 MHz (ATtiny22L)
– 0 - 8 MHz (ATtiny22)
8-bit
Microcontroller
with 2K Bytes of
In-System
Programmable
Flash
ATtiny22
ATtiny22L
Preliminary
Description
The ATtiny22/L is a low-power CMOS 8-bit microcontrollers based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the ATtiny22/L
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to
optimize power consumption versus processing speed.
Pin Configuration
PDIP/SOIC
RESET 1
(CLOCK) PB3 2
PB4 3
GND 4
8 VCC
7 PB2 (SCK/T0)
6 PB1 (MISO/INT0)
5 PB0 (MOSI)
Rev. 1273A–04/99
1
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