5962-9452405MLA データシートの表示（PDF） - Atmel Corporation
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5962-9452405MLA Datasheet PDF : 14 Pages
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Preload of Registered Outputs
The ATV750's registers are provided with circuitry to allow
loading of each register asynchronously with either a high
or a low. This feature will simplify testing since any state
can be forced into the registers to control test sequencing.
A VIH level on the I/O pin will force the register high; a VIL
will force it low, independent of the output polarity. The pre-
load state is entered by placing an 10.5V to 11.5V signal on
pin 8 on DIPs, and pin 10 on SMPs. When the clock term is
pulsed high, the data on the I/O pin is placed into the regis-
ter chosen by the Select Pin.
Level forced on registered output pin
during PRELOAD cycle
VIH
VIL
VIH
VIL
Select
Pin State
Low
Low
High
High
Register #1 state
after cycle
High
Low
X
X
Register#2 State
after cycle
X
X
High
Low
Power-Up Reset
The registers in the ATV750(L) are designed to reset dur-
ing power up. At a point delayed slightly from VCC crossing
3.8V, all registers will be reset to the low state. The output
state will depend on the polarity of the output buffer.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock term
high, and
3. The signals from which the clock is derived must
remain stable during tPR.
Pin Capacitance (f = 1 MHz, T = 25°C)(1)
Parameter Description Min
tPR
Power-Up
Reset Time
Typ Max
600 1000
Typ
Max
Units
Conditions
CIN
COUT
Note:
5
8
pF
VIN = 0V
6
8
pF
VOUT = 0V
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Units
ns
8
ATV750/L
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