5962-9452403MLA データシートの表示（PDF） - Atmel Corporation
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5962-9452403MLA Datasheet PDF : 14 Pages
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ATV750/L
Using the ATV750's Many Advanced Features
The ATV750's flexibility puts more usable gates in 24-pins
than other PLDs. The ATV750(L) starts with an architecture
similar to the popular AT22V10, and adds several features:
• Asynchronous Clocks -
Each of the flip-flops in the ATV750(L) has a dedicated
product term driving the clock. The user is no longer
constrained to using one clock for all the registers.
Buried state machines, counters, and registers can all
coexist in one device, while running on separate clocks.
The ATV750(L) clock period matches that of similar
synchronous devices.
• A Full Bank of 10 More Registers -
The ATV750(L) provides two flip-flops for each output
macrocell - a total of 20. Each register has its own clock
and reset product terms, as well as its own SUM term.
• Independent I/O Pin and Feedback Paths -
Each I/O pin on the ATV750(L) has a dedicated input
path. Each of the 20 registers has individual feedback
terms into the array. This feature, combined with
individual product terms for each I/O's output enable,
facilitates designs using bi-directional I/O buses.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATV750(L) fuse patterns. Once programmed, the
output buffers will remain in a high impedance state during
verify.
The security fuse should be programmed last, as its effect
is immediate.
Erasure Characteristics
The entire memory array of an ATV750(L) is erased after
exposure to ultraviolet light at a wavelength of 2537 Å.
Complete erasure is assured after a minimum of 20 min-
utes exposure using 12,000 µW/cm2 intensity lamps
spaced one inch away from the chip. Minimum erase time
for lamps at other intensity ratings can be calculated from
the minimum integrated erasure dose of 15 W•sec/cm2. To
prevent unintentional erasure, an opaque label is recom-
mended to cover the clear window on any UV erasable
PLD which will be subjected to continuous fluorescent
indoor lighting or sunlight.
• Combinable Sum Terms -
Each output macrocell’s two SUM terms can be
combined in an OR gate before the output or the register.
This provides up to 16 product terms per output or flip-
flop. This architecture increases the number of usable
gates available.
Atmel CMOS PLDs
Atmel’s Programmable Logic Devices utilize an advanced
1.5-micron CMOS EPROM technology. This technology's
state of the art features are the optimum combination for
PLDs:
Programming Software Support
• CMOS technology provides high speed, low power, and
high noise immunity.
Software which is capable of transforming Boolean equa-
tions, state machine descriptions and truth tables into
JEDEC files for the ATV750(L) is available from several
PLD software vendors. Please refer to the Software Sup-
port Information table in the Programmable Logic Develop-
ment Tools section for more information.
Synchronous Preset and
Asynchronous Reset
One synchronous preset line is provided for all 20 registers
in the ATV750(L). The appropriate input signals to cause
the internal clocks to go to a high state must be received
during a synchronous preset. Appropriate setup and hold
times must be met, as shown in the switching waveform
diagram.
• EPROM technology is the most cost effective method for
producing PLDs - surpassing bipolar fusible link
technology in low cost, while providing the necessary
reprogrammability.
• EPROM reprogrammability, which is 100% tested before
shipment, provides inherently better programmability and
reliability than one-time fusible PLDs.
• Atmel's EPROM process has proven extremely reliable
in the volume production of a full line of advanced
EPROM memory products, from 64K to one-megabit
devices.
An individual asynchronous reset line is provided for each
of the 20 flip-flops. Both master and slave halves of the flip-
flops are reset when the input signals received combine so
as to force the internal resets high.
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