A8905CLB データシートの表示（PDF） - Allegro MicroSystems
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A8905CLB Datasheet PDF : 12 Pages
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8905
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
acquire and minimizes settling. The Current Control Block Diagram illustrates
the YANK signal and its effects.
Braking. A dynamic braking feature of the A8905CLB shorts the three
motor windings to ground. This is accomplished by turning the three source
drivers OFF and the three sink drivers ON. Activation of the brake can be
implemented through the BRAKE input or through the D2 bit in the serial port.
The supply voltage for the brake circuitry is the CRES voltage, allowing the brake
function to remain active after power failure. Power-down braking with delay can
be implemented by using an external RC and other components to control the
brake terminal, as shown. Brake delay can be set using the equation below to
ensure that voice-coil head retract occurs before the spindle motor brake is
activated. Once the brake is activated, due to the inherent capacitive input, the
three sink drivers will remain active until the device is reset.
Centertap. The A8905CLB internally
simulates the centertap voltage of the motor.
To obtain reliable start-up performance from
motor to motor, the motor centertap should be
connected to this terminal.
Serial Port. The serial port functions to
write various operational and diagnostic modes
to the A8905CLB. The serial port DATA IN is
enabled/disabled by the CHIP SELECT
terminal. When CHIP SELECT is high the
serial port is disabled and the chip is not
affected by changes in data at the DATA IN or
CLOCK terminals.
FAULT
BYPASS
VRET
FAULT
RB
tBRK = RBCB 1 – ln
VBRK
VFAULT - VD
BRAKE
V FAULT – V D
BRAKE
ACTIVATED
CB
RB
t BRK
VBRK
Dwg. OP-004
V
BB
1
VBB
COMMUTATION
DELAY
24
2
23
C D2
3
22
CWD
4
21
C ST
CD1
DATA IN
CLOCK
CHIP SELECT
To write data to the serial port, the
CLOCK terminal should be low prior to the
CHIP SELECT terminal going low. Once
CHIP SELECT goes low, information on the
DATA IN terminal is read into the shift register
on the positive-going transition of the CLOCK.
There are 24 bits in the serial input port.
Data written into the serial port is latched
and becomes active upon the low-to-high
transition of the CHIP SELECT terminal at the
end of the write cycle. D0 will be the last bit
written to the serial port.
Reset. The RESET terminal (when pulled
low) clears all serial port bits, including the D0
latch, which puts the A8905CLB in the sleep
mode.
5
20
RESET
6
19
TYPICAL
APPLICATION
7
18
BYPASS
8
MUX
17
DATA OUT
99
FLL
16
OSC (REF)
10
CB
11
12
CRES
0.22 µF
BOOST
CHARGE
PUMP
VDD 15
14
13
+5 V
INDEX
R F1 CF1
CF2
Dwg. EP-036-1
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