BD12KA5W(2009) データシートの表示（PDF） - ROHM Semiconductor
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BD12KA5W Datasheet PDF : 10 Pages
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BD□□KA5,BD□□KA5W Series,BD00KA5W Series
Technical Note
●Other Caution
○Protection Circuits
Over-current Protection Circuit
A built-in over-current protection circuit corresponding to the current capacity prevents the destruction of the IC when
there are load shorts. This protection circuit is a “7”-shaped current control circuit that is designed such that the current
is restricted and does not latch even when a large current momentarily flows through the system with a high-capacitance
capacitor. However, while this protection circuit is effective for the prevention of destruction due to unexpected accidents,
it is not suitable for continuous operation or transient use. Please be aware when creating thermal designs that the
over-current protection circuit has negative current capacity characteristics with regard to temperature.
○Thermal Shutdown Circuit (Thermal Protection)
This system has a built-in temperature protection circuit for the purpose of protecting the IC from thermal damage. As
shown in Fig. 20-22, this must be used within the range of acceptable loss, but if the acceptable loss is continuously
exceeded, the chip temperature Tj increases, causing the thermal shutdown circuit to operate. When the thermal
shutdown circuit operates, the operation of the circuit is suspended. The circuit resumes operation immediately after the
chip temperature Tj decreases, so the output repeats the ON and OFF states (Please refer to Figs.12 for the temperatures
at which the temperature protection circuit operates).
There are cases in which the IC is destroyed due to thermal runaway when it is left in the overloaded state. Be sure to
avoid leaving the IC in the overloaded state.
○Reverse Current
In order to prevent the destruction of the IC when a reverse current flows through the IC, it is recommended that a diode
be placed between the Vcc and Vo and a pathway be created so that the current can escape (Refer to Fig.27).
Reverse current
Vcc
OUT
CTL
GND
Fig.27 : Bypass diode
○This IC is BI-CMOS IC that has a P-board (substrate) and P+ isolation between each element, as shown in Fig.28. A P-N
junction is formed between this P-layer and the N-layer of each element, and the P-N junction operates as :
- a parasitic diode when the electric potential relationship is GND> Terminal A, GND> Terminal B, or
- a parasitic transistor when the electric potential relationship is Terminal B > GND> Terminal A.
Parasitic elements are structurally inevitable in the IC. The operation of parasitic elements induces mutual interference
between circuits, causing malfunctions and eventually the destruction of the IC. Take precaution as not to use the IC in
ways that would cause parasitic elements to operate. For example, applying a voltage that is lower than the GND
(P-board) to the input terminal.
Transistor (NPN)
(Pin B) O
B
E
(Pin A)
P+
N
N
P
N
P
GND
P+
N
P+
N
P
Parasitic element
or transistor
GND
Resistor
P
N
P+
N
Parasitic element
GND
(Pin B)
BC
E
GND
Parasitic element
or transistor
(Pin A)
Parasitic element
GND
Fig. 28 : Basic structure example
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2009.04 - Rev.A
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