BD5340(2013) データシートの表示（PDF） - ROHM Semiconductor
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BD5340 Datasheet PDF : 16 Pages
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BD52xx series BD53xx series
Datasheet
●Application Information
Explanation of Operation
For both the open drain type (Fig.15) and the CMOS output type (Fig.16), the detection and release voltages are used as
threshold voltages. When the voltage applied to the VDD pins reaches the applicable threshold voltage, the VOUT terminal
voltage switches from either “High” to “Low” or from “Low” to “High”. Please refer to the Timing Waveform and Electrical
Characteristics for information on hysteresis. Because the BD52xx series uses an open drain output type, it is necessary to
connect a pull-up resistor to VDD or another power supply if needed [The output “High” voltage (VOUT) in this case becomes
VDD or the voltage of the other power supply].
VDD
VDD
R1
Vref
VDD
RL
VOUT
RESET
R1
Vref
Q2
VDD
RESET
R2
Q1
R2
VOUT
Q3
R3
Q3
Q1
R3
GND
GND
CT
Fig.15 (BD52xxType Internal Block Diagram)
CT
Fig.16 (BD53xxType Internal Block Diagram)
Setting of Detector Delay Time
It is possible to set the delay time at the rise of VDD using a capacitor connected to the Ct terminal.
Delay time at the rise of VDD tPLH：Time until when Vout rise to 1/2 of VDD after VDD rise up and beyond the release
voltage(VDET+∆VDET)
tPLH = -CCT×RCT×ln
VDD-VCTH
VDD
CCT:
RCT:
VCTH:
ln :
CT pin External Capacitance
CT pin Internal Impedance（Please refer to Electrical Characteristics.）
CT pin Threshold Voltage（Please refer to Electrical Characteristics.）
Natural Logarithm
Reference Data of Falling Time (tPHL) Output
Examples of Falling Time (tPHL) Output
Part Number
tPHL[µs] -40°C
tPHL[µs] ,+25°C
tPHL[µs],+105°C
BD5227
30.8
30
28.8
BD5327
26.8
26
24.8
*This data is for reference only.
The figures will vary with the application, so please confirm actual operating conditions before use.
Timing Waveforms
Example: the following shows the relationship between the input voltage VDD, the CT Terminal Voltage VCT and the output
voltage VOUT when the input power supply voltage VDD is made to sweep up and sweep down (The circuits are those in
Figure.15 and 16).
VDD
VDET+ΔVDET
VDET
VOPL
0V
VCT
1/2 VDD
1 When the power supply is turned on, the output is unstable
from after over the operating limit voltage (VOPL) until tPHL.
Therefore it is possible that the reset signal is not outputted when
⑤
the rise time of VDD is faster than tPHL.
2 When VDD is greater than VOPL but less than the reset release
voltage (VDET+∆VDET), the CT terminal (VCT) and output (VOUT)
voltages will switch to L.
3 If VDD exceeds the reset release voltage (VDET+∆VDET), then
VOUT switches from L to H (with a delay due to the CT terminal).
4 If VDD drops below the detection voltage (VDET) when the
power supply is powered down or when there is a power supply
VOUT
tPHL
tPLH
tPLH
fluctuation, VOUT switches to L (with a delay of tPHL).
5 The potential difference between the detection voltage and the
tPHL
release voltage is known as the hysteresis width (∆VDET). The
system is designed such that the output does not toggle with
①② ③ ④
power supply fluctuations within this hysteresis width, preventing
Fig.17 Timing Waveform
malfunctions due to noise.
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© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
10/13
TSZ02201-0R7R0G300040-1-2
22.May.2013 Rev.006
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