BL7430EC データシートの表示（PDF） - Shanghai Belling Co., Ltd.
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BL7430EC Datasheet PDF : 4 Pages
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BL7430EC 104-bit EEPROM Smart
Counter Circuit
BL7430EC circuits consists of 104 bits EEPROM. The whole storing area is divided into three
areas according to different usage.
• Organization of Memory
Pin No.
Address
Memory Type
1
0~15
ROM
2
16~63
PROM
64
PROM
3
65~71
PROM
72~103
EEPROM
Function
Manufacturer code
Card Data
Control flag
Uppermost non-erasable counter stage; up to
3 bits(69~71) already canedled by testing
upon delivery
Count range
Mentioned above is the user mode after card
being personalized. When chips are transferred
to card-manufacturer, they are in issue mode,
after being personalized, then changed to user
mode. The differences between issue mode
and user mode are presented on the right
figure.
Counting Method
The counting area consists of 36 bits EEPROM. The structure of counter is 5-stage with 8 bits ,
each stage like an abcus, but the highest stage has only 4 bits, the counting scope is 20480,while
counting, the first stage is erased after writing any bit of the second counting stage, all do like
this, then the fourth counting stage is erased after writing any bit of the fifth stage. But the fifth
counting stage can be erased, so the contents of counting cells are continuously reduced to zero.
In one counting stage, if the writable numbers more than the number which should be written, this
can be operated without any problem. If the writable number is less than the number should be
written, we can do like this: first write each writable number of this stage, then we write on bit of
higher stage and erase 8 bits of current stage. Thus we can write the remaining number in current
stage.
• Reading/Writing operation
Reading operation
Internal address-counter works following bit clock, at the clock rising edge and RST is low ,the
address-counter add 1 after the clock falling edge, the content of the relative address is output to
I/O port. Both CLK and RST are high , the address-counter is reset to 0.
tR
RST
td1
tr
td2
tf
tH
CLK
td3
tL
td4
IO
DO0
DO1
Add
A0
A1
A2
Setting Address and Readout
http://www.belling.com.cn
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Total 4 Pages
8/16/2006
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