BL7430EC データシートの表示（PDF） - Shanghai Belling Co., Ltd.
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BL7430EC Datasheet PDF : 4 Pages
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BL7430EC 104-bit EEPROM Smart
Counter Circuit
Writing operation
When RST=1 and CLK=0, we set R mark, under this condition if next clock pulse comes the
address-counter will not increase and go into writing operation during the clock high level. The
address-counter is re-effective and writing is finished at the clock falling edge. During the issue
mode, R mark is useless to the cells of manufacturer code area; during the user mode, R mark
is useless to the cells of code area for both manufacturer and issuer.
ts
RST
td5
td6
td7
CLK
tHW
Add n
n+1
n+2
IO n
n+1
n+1
Write Address
Erasing operation
Erasing operation to any stage will lead to the automatic erasing of next lower stage.
tS
tS
RST
td6
td7
CLK
tHW
tHE
Add
n
n+1
IO n
n
n
Erasing 8 Bits with Carry
Power on and reset
The address is reset after power on. RST keep”1” and must last longer than one clock cycle.
When RST is changed to low level, the content in the “0” address is shown on I/O port. The
unstability of VCC also can induce the address reset .
About Comparison of Transmission Password
Password comparison must be executed immediately after write “0” operation
RST
CLK
tHW
ADDRESS 0
1
EC(LSB-1)
~EC(MSB-1)
I/O
D0
EC bit addr
Bit output Write one bit EC
80
81
82
td8 D8
td9
D8
D8
0
1
2
103 104
td10
D103
• Package
Module package, the module type according to customer demand.
http://www.belling.com.cn
-3-
Total 4 Pages
8/16/2006
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