BL7448SM Intelligent 8K-bit
EEPROM
After security code identification , I/O will be changed from H to L. I/O will return to H when RST change
from L to H. EC cannot be erased automatically.
Write Error Counter (EC)
Before security code identification, only Error Counter (EC) can be written. A number of erased bit of EC
means what times EC can be written. After security code verification is successful, EC should be erased
before power off. After security code verification is unsuccessful, if it is verified again, EC must be written.
Input PSC
PSC input start from lowest bit of low byte to high byte. If comparison of data is right, EEPROM can be
written or erased before power-off and the corresponding protection bit of PSC is H, PSC can be changed.
Write EC
No
compare
fobidden
EC write
Enable?
Yes
compare 1st PSC
Byte
No
compare
failed
OK?
Yes
compare 2nd PSC
Byte
No
Command Input
compare
Failed
OK?
Yes
Password
Verification
OK,Erase EC->FF
Figure 9 Verification Procedure
Data
Output
RST
CLK 0
23
I/O
A8 A9 D6 D7 0 1 2 3 4 5 6 7 P0 0 1 2 3 4 5 6 7 P0 P0 0 1 2 3 4 5 6 7 P0
Starting Address
random
value
Starting Address
Starting Address +1
Figure 10. PSC Verification timing
Starting Address + n
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Total 7 Pages
8/16/2006